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128 - position i 2 c- compatible digital potentiometer data sheet ad5247 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change witho ut notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106 , u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2003 C 2012 analog devices, inc. all rights reserved. features 128 position s end - to - end resistance: 5 k?, 10 k?, 50 k?, 100 k? ultracompact, sc70 - 6 (2 mm 2.1 mm) package i 2 c - compatible interface full read/write of wiper register power - on preset to midscale single - supply 2.7 v to 5.5 v rheostat mode temperat ure coefficient: 45 ppm/c low power, i dd = 0.9 a at 3.3 v typical wide operating temperature range : ? 40c to +125c applications mechanical potentiometer replacement in new designs transducer adjustment of pressure, temperature, position, chemical, and o ptical sensors rf amplifier - biasing lcd brightness and contrast adjustment automotive electronics adjustment gain control and offset adjustment functional block dia gram i 2 c interface wiper register scl sda gnd v dd a w b 03876-001 figure 1. general description the ad5247 provides a compa ct, 2 mm 2.1 mm , packaged solution for 128 - position adjustment applications. this device performs the same electronic adjustment function as a mechanica l potentiometer or a variable resistor. available in four different end - to - end resistance values (5 k?, 10 k?, 50 k?, and 100 k?), these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments. the wiper settings are controllable through the i 2 c - compatible digital inte rface, which can also be used to read back the present wiper register control w ord. the 10 k and 100 k options each have three hard - coded slave address options available to allow users access to three of these devices on one i 2 c bus (see table 8 for a full list of slave address locations). the resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code tr ansferred into the rdac latch. note the terms digital potentiome ter, vr (variable resistor) , and rdac are used in terchangeably in this document. operating from a 2.7 v to 5.5 v power supply and consuming 0.9 a (3.3 v) allows the ad5247 to be used in portable battery - operated applications.
ad5247 data sheet rev. f | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 5 k? version .................................. 3 electrical characteristics 10 k?, 50 k?, and 100 k? ve rsions .......................................................................................... 4 timing characteristics 5 k?, 10 k?, 50 k?, and 100 k? ve rsions .......................................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 test circuits ..................................................................................... 12 i 2 c interface .................................................................................... 13 theory of operation ...................................................................... 14 pr ogramming the variable resistor ......................................... 14 programming the potentiometer divider ............................... 15 i 2 c - compatible 2 - wire serial bus ........................................... 15 level shifting for bidirectional interface ................................ 16 esd protection ........................................................................... 16 terminal voltage operating range ......................................... 16 maximum operating current .................................................. 16 power - up sequence ................................................................... 16 layout and power supply bypassing ....................................... 17 constant bias to retain resistance setting ............................. 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 5/12 rev. e to rev. f change s to features and general description sections .............. 1 changes to i dd parameters, table 1 ................................................ 3 changes to i dd parameter s, table 2 ................................................ 4 changes to figure 15 ........................................................................ 9 changes to figure 16 ...................................................................... 10 removed evaluation board section ............................................. 17 changes to ordering guide .......................................................... 18 1/11 rev. d to rev. e change to ta ble 1, added output logic low .............................. 3 change to tabl e 2, added output logic low .............................. 4 3/10 rev. c to rev. d changes to table 9 and table 10 ................................................... 1 4 10 /09 rev. b to rev. c changes to zero - scale error (10 k?) p arameter, table 2 ........... 4 changes to ordering guide .......................................................... 18 3 /0 7 rev. a to rev. b changes to general description section ....................................... 1 added table 8 ................................................................................. 13 changes to i 2 c - compati ble 2 - wi re serial bus section ............ 15 changes to ordering guide .......................................................... 18 7/06 rev. 0 to rev. a updated format .................................................................. universal changes to absolute maximum ratings section .......................... 6 changes to ordering guide .......................................................... 18 9/03 revision 0: initial version
data sheet ad5247 rev. f | page 3 of 20 specifications electrical characteristics5 k version v dd = 5 v 10% or 3 v 10%, v a = v dd , ?40c < t a < +125c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ?1.5 0.1 +1.5 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect ?4 0.75 +4 lsb nominal resistor tolerance 3 ?r ab ?30 +30 % resistance temperature coefficient 3 ?r ab /?t 45 ppm/c output resistance r wb code = 0x00 75 300 dc characteristicspotentiometer divider mode differential nonlinearity 4 dnl ?1 0.1 +1 lsb integral nonlinearity 4 inl ?1 0.2 +1 lsb voltage divider temperature coefficient ?v w /?t code = 0x40 15 ppm/c full-scale error v wfse code = 0x7f ?3 ?2 0 lsb zero-scale error v wzse code = 0x00 0 1 2 lsb resistor terminals voltage range 5 v a, v w gnd v dd v capacitance a 6 c a f = 1 mhz, measured to gnd, code = 0x40 45 pf capacitance w 6 c w f = 1 mhz, measured to gnd, code = 0x40 60 pf common-mode leakage i cm v a = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf output logic low (sda) v ol i ol = 3 ma 0.4 v i ol = 6 ma 0.6 v power supplies power supply range v dd range 2.7 5.5 v supply current i dd v dd = 5.5 v; v ih = v dd or v il = gnd 3 7 a v dd = 5 v; v ih = v dd or v il = gnd 2.5 5.2 a v dd = 3.3 v; v ih = v dd or v il = gnd 0.9 2 a power dissipation 7 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 40 w power supply sensitivity pssr v dd = 5 v 10%, code = midscale 0.003 0.05 %/% dynamic characteristics 6, 8 bandwidth C3 db bw_5 k r ab = 5 k, code = 0x40 1.2 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = 5 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 2.5 k, r s = 0 6 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v a = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w, with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are gua ranteed monotonic under operating conditions. 5 resistor terminal a and resistor terminal w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 8 all dynamic characteristics use v dd = 5 v.
ad5247 data sheet rev. f | page 4 of 20 electrical character istics 10 k ?, 50 k ?, and 100 k ? versions v dd = 5 v 10% or 3 v 10%, v a = v dd , ? 40c < t a < +125c, unless otherwise noted. table 2 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r - dnl r wb , v a = no connect ? 1 0.1 +1 lsb resistor integral nonlinearity 2 r - inl r wb , v a = no connect ? 2 0.25 +2 lsb nominal resistor tolerance 3 ?r ab ? 20 +20 % resistance temperature coefficient 3 ?r ab /?t 45 ppm/c output resistance r wb code = 0x00 75 300 ? dc characteristics potentiometer divider m ode differential nonlinearity 4 dnl ? 1 0.1 +1 lsb integral nonlinearity 4 inl ? 1 0.2 +1 lsb voltage divider temperature coefficient ?v w /?t code = 0x40 15 ppm/c full - scale error (50 k?, 100 k?) v w fse code = 0x7f ? 1 ? 1 0 lsb zero - scale error (50 k?, 100 k?) v wzse code = 0x00 0 0.4 1 lsb full - scale error (10 k?) v wfse code = 0x7f ? 2 ? 0.5 0 lsb zero - scale error (10 k?) v wzse v dd = 4.5 v to 5.5 v , code = 0x00 0 0.5 1 lsb v dd = 2.7 v to 4.4 v , cod e = 0x00 0 0.5 1.2 lsb resistor terminals voltage range 5 v a, v w gnd v dd v capacitance a 6 c a f = 1 mhz, measured to gnd, code = 0x40 45 pf capacitance w 6 c w f = 1 mhz, measured to gnd, code = 0x40 60 pf common - mode leakage i cm v a = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input curren t i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf output logic low (sda) v ol i ol = 3 ma 0.4 v i ol = 6 ma 0.6 v power supplies power supply range v dd range 2.7 5.5 v supply curren t i dd v dd = 5.5 v; v ih = v dd or v il = gnd 3 7 a v dd = 5 v; v ih = v dd or v il = gnd 2.5 5.2 a v dd = 3 .3 v; v ih = v dd or v il = gnd 0.9 2 a power dissipation 7 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 40 w power supply sensitivity pssr v dd = 5 v 10%, code = midscale 0.01 0.02 %/%
data sheet ad5247 rev. f | page 5 of 20 parameter symbol conditions min typ 1 max unit dynamic characteristics 6 , 8 bandwidth C 3 db bw r ab = 10 k?/50 k?/100 k?, code = 0x40 600/100/40 khz total harmonic distortion thd w v a =1 v rms, f = 1 khz, r ab = 10 k? 0.05 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v 1 lsb error band 2 s resistor noise voltage density e n_wb r wb = 5 k?, r s = 0 9 nv/hz 1 typical specifications represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error r - inl is the deviat ion from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v a = v dd , wiper (v w ) = no con nect. 4 inl and dnl are measured at v w, with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor termin al a and resistor terminal w have no limitations on polarity with respect to each other. 6 guaranteed by design, not subject to production test. 7 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 8 all dyna mic characteristics use v dd = 5 v. timing characteristi cs 5 k ?, 10 k ?, 50 k ?, and 100 k ? versions v dd = 5 v 10% or 3 v 10%, v a = v dd , ? 40c < t a < +125c, unless otherwise noted. table 3 . parameter 1 , 2 , 3 symbol min typ 4 max unit scl clock frequency f scl 400 khz bus free time between stop and start, t buf t 1 1.3 s hold time (repeated s tart), t hd;sta 5 t 2 0.6 s low period of scl clock, t low t 3 1.3 s high period of scl clock, t high t 4 0.6 50 s setup time for repeated start condition, t su;sta t 5 0.6 s data hold time, t hd; dat t 6 0.9 s data setup time, t su; dat t 7 100 ns fall time of both sda and scl signals, t f t 8 300 ns rise time of both sda and scl signals, t r t 9 300 ns setup time for stop condition, t su;sto t 10 0.6 s 1 specifications apply to all parts. 2 guaranteed by design, not subject to production test. 3 see timing diagrams ( figure 2 , figure 33 , and figure 34 ) for locations of measured values. 4 typical specifications represent average readings at 25c and v dd = 5 v. 5 after this period, the first clock pulse is generated. t 7 t 8 t 9 p s p s t 10 t 5 t 9 t 8 scl sda t 6 03876-031 t 1 t 2 t 3 t 4 t 2 figure 2. i 2 c interface, detailed timing diagram
ad5247 data sheet rev. f | page 6 of 20 absolute max imum ratings t a = 25c, unless otherwise noted. table 4 . parameter rating v dd to gnd C 0.3 v to +7 v v a , v w to gnd v dd terminal current, ax to bx, ax to wx, bx to wx pulsed 1 20 ma continuous 5 ma digital inputs and output voltage to gnd 0 v to v dd + 0.3 v operating temperature range C 40c to +125c maximum junction temperature (t jmax ) 150c storage temperature range C 65c to +150c thermal resistance ja 2 : (sc70 -6) 340c/w re flow soldering peak temperature snpb 240c pb - free 260c 1 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 package power dissipation = (t jmax C t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet ad5247 rev. f | page 7 of 20 pin configuration an d function descripti ons v d d 1 g n d 2 sc l 3 a 6 w 5 sd a 4 ad 524 7 t o p vi ew (n o t to sca l e ) 03876-043 figure 3 . pin configuration table 5 . pin function descriptions pin o. mneonic description 1 v dd positive power supply. 2 gnd digital g round and b termination voltage. 3 scl serial clock input; positive edge triggered. 4 sda serial data input/output. 5 w terminal w. 6 a terminal a.
ad5247 data sheet rev. f | page 8 of 20 typical performance characteristics c o d e (d ec i mal ) rheostat mode inl (lsb) 0 ?1 . 0 0 0 . 2 1 . 0 1 6 3 2 4 8 6 4 8 0 9 6 11 2 12 8 ?0 . 8 ?0 . 6 ?0 . 4 ?0 . 2 0 . 4 0 . 6 0 . 8 v d d = 2 . 7 v v d d = 5 . 5 v t a = 2 5 c r a b = 10 k ? rheostat mode inl (lsb) 03876-002 figure 4. r - inl vs. code vs. supply v oltages c o d e (d ec i mal ) rheostat mode dnl (lsb) 0 ?0 . 5 ?0 . 4 ?0 . 3 ?0 . 2 1 6 3 2 4 8 6 4 8 0 9 6 11 2 12 8 ?0 . 1 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 v d d = 2 . 7 v v d d = 5 . 5 v t a = 2 5 c r a b = 10 k ? 03876-003 figure 5. r - dnl vs. code vs. supply voltages c o d e (d e c i m a l ) 0 ? 0 . 2 5 0 0 . 0 5 0 . 2 5 1 6 3 2 4 8 6 4 8 0 9 6 1 1 2 1 2 8 ? 0 . 2 0 ? 0 . 1 5 ? 0 . 1 0 ? 0 . 0 5 0 . 1 0 0 . 1 5 0 . 2 0 v d d = 2 . 7 v r a b = 1 0 k ? potentiometer mode inl (lsb) t a = ? 4 0 c t a = +2 5 c t a = +8 5 c t a = +1 2 5 c t a = ? 4 0 c t a = +2 5 c , + 8 5 c , + 1 2 5 c 03876-004 figure 6 . inl vs. code vs. temperature c o d e (d ec i mal ) potentiometer mode dnl (lsb) 0 ?0 . 2 5 ?0 . 2 0 ?0 . 1 5 ?0 . 1 0 1 6 3 2 4 8 ?0 . 0 5 0 0 . 0 5 0 . 1 0 0 . 1 5 0 . 2 0 0 . 2 5 6 4 8 0 9 6 11 2 12 8 t a = ?4 0 c , +2 5 c , +8 5 c , +12 5 c ?4 0 c +2 5 c +8 5 c +12 5 c v d d = 2 . 7 v r a b = 10 k ? 03876-005 figure 7 . dnl vs. code vs. temperature c o d e (d ec i mal ) 0 ?0 . 2 5 0 0 . 0 5 0 . 2 5 1 6 3 2 4 8 6 4 8 0 9 6 11 2 12 8 ?0 . 2 0 ?0 . 1 5 ?0 . 1 0 ?0 . 0 5 0 . 1 0 0 . 1 5 0 . 2 0 v d d = 2 . 7 v v d d = 5 . 5 v t a = 2 5 c r a b = 10k ? potentiometer mode inl (lsb) 03876-006 figure 8. inl vs. code vs. supply voltages c o d e (d ec i mal ) 0 ?0 . 2 5 0 0 . 0 5 0 . 2 5 1 6 3 2 4 8 6 4 8 0 9 6 11 2 12 8 ?0 . 2 0 ?0 . 1 5 ?0 . 1 0 ?0 . 0 5 0 . 1 0 0 . 1 5 0 . 2 0 t a = 2 5 c r a b = 10 k ? potentiometer mode dnl (lsb) v d d = 2 . 7 v v d d = 5 . 5 v v d d = 2 . 7 v v d d = 5 . 5 v 03876-007 figure 9 . dnl vs. code vs. supply voltages
data sheet ad5247 rev. f | page 9 of 20 c o d e (d ec i mal ) rheostat mode inl (lsb) 0 ?1 . 0 ?0 . 8 ?0 . 6 ?0 . 4 1 6 3 2 4 8 ?0 . 2 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 6 4 8 0 9 6 11 2 12 8 t a = ?4 0 c t a = +2 5 c t a = +8 5 c t a = +12 5 c t a = ?4 0 c t a = +8 5 c t a = +2 5 c t a = +12 5 c 03876-008 figure 10 . r - inl vs. code vs. temperature c o d e (d ec i mal ) rheostat mode dnl (lsb) 0 ?0 . 5 ?0 . 4 ?0 . 3 ?0 . 2 1 6 3 2 4 8 ?0 . 1 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 6 4 8 0 9 6 11 2 12 8 t a = ?4 0 c , +2 5 c , +8 5 c , +12 5 c ?4 0 c +2 5 c +8 5 c +12 5 c v d d = 2 . 7 v r a b = 10 k ? 03876-009 figure 11 . r - dnl vs. code vs. temperature temperature ( c ) rheostat mode inl (lsb) ?40 ?3.0 ?0.5 0 ?25 ?10 5 20 35 50 65 80 ?2.5 ?2.0 ?1.5 ?1.0 full-scale error (lsb) 95 110 125 v dd = 5.5v, v a = 5.5v v dd = 2.7v, v a = 2.7v 03876-010 figu re 12 . full - scale error vs. temperature temperature ( c ) zero-scale error (lsb) ?40 0 0.25 0.50 0.75 ?25 ?10 5 1.00 1.25 1.50 20 35 50 65 80 95 110 125 v dd = 5.5v, v a = 5.5v v dd = 2.7v, v a = 2.7v 03876-011 figure 13 . zero - scale error vs. temperature t empera t ur e ( c ) i dd, supply current (a) ?4 0 0 . 0 1 0 . 1 1 1 0 ?2 5 ?1 0 10 0 5 2 0 3 5 5 0 6 5 8 0 9 5 11 0 12 5 v d d = 5 . 5 v v d d = 2 . 7 v d igi t a l i n pu t s = 0 v c o d e = 0x4 0 03876-012 figure 14 . supply current vs. temperature 0 10 20 30 40 50 60 70 80 90 100 1 9 17 25 33 41 49 57 65 73 81 89 97 105 1 13 121 rthesos ta t mode tempco (ppm/c) code (decimal) 5v 2.7v 03876-013 i wb = 200 a r ab = 10k figure 15 . ? r wb / ?t vs. code
ad5247 data sheet rev. f | page 10 of 20 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 1 10 19 28 37 46 55 64 73 82 91 100 109 1 18 127 potentiometer mode tempco (ppm/c) code (decimal) 2.7v 5v v a = v dd r ab = 10k 03876-014 figure 16 . ? v wb / ?t vs. code gain (db) 10 k ? 6 ?1 2 ?1 8 ?2 4 ?3 0 ?3 6 0 ?4 2 ?5 4 100 k 1 m 10 m ?6 0 0x4 0 1 k ?4 8 0x2 0 0x1 0 0x0 8 0x0 4 0x0 2 0x0 1 f r eq u enc y (h z) 03876-015 figure 17 . gain vs. frequency vs. code, r ab = 5 k ? 10 k ? 6 ?1 2 ?1 8 ?2 4 ?3 0 ?3 6 0 ?4 2 ?5 4 100 k 1 m 10 m ?6 0 0x4 0 1 k ?4 8 0x2 0 0x1 0 0x0 8 0x0 4 0x0 2 0x0 1 gain (db) f r eq u enc y (h z) 03876-016 figure 18 . gain vs. frequency vs. code, r ab = 10 k ? 10 k ? 6 ?1 2 ?1 8 ?2 4 ?3 0 ?3 6 0 ?4 2 ?5 4 100 k 1 m 10 m ?6 0 0x4 0 1 k ?4 8 0x2 0 0x1 0 0x0 8 0x0 4 0x0 2 0x0 1 gain (db) f r eq u enc y (h z) 03876-017 figure 19 . gain vs. frequency vs. code, r ab = 50 k ? 10 k ? 6 ?1 2 ?1 8 ?2 4 ?3 0 ?3 6 0 ?4 2 ?5 4 100 k 1 m 10 m ?6 0 0x4 0 1 k ?4 8 0x2 0 0x1 0 0x0 8 0x0 4 0x0 2 0x0 1 gain (db) f r eq u enc y (h z) 03876-018 figure 20 . gain vs. frequency vs. code, r ab = 100 k ? 10 k ? 6 ?1 2 ?1 8 ?2 4 ?3 0 ?3 6 0 ?4 2 ?5 4 100 k 1 m 10 m ?6 0 5k ? 1 k ?4 8 50k ? 10k ? 100k ? gain (db) f r eq u enc y (h z) 03876-019 figure 21 . ?3 db bandwidth @ code = 0x80
data sheet ad5247 rev. f | page 11 of 20 frequency (hz) i dd (a) 1k 0.25 0.20 0.15 0.30 0.10 0.05 10k 100k 1m 0 c t a = 25c a-v dd = 5.5v code = 0x55 b-v dd = 5.5v code = 0x7f c-v dd = 2.7v code = 0x55 d-v dd = 2.7v code = 0x7f d b a 03876-020 figure 22 . i dd vs. frequency wiper resistance (?) c o d e (d ec i mal ) 0 12 5 10 0 7 5 15 0 5 0 2 5 1 6 8 0 12 8 0 t a = 25 c r a b = 5 0 k? v d d = 2 . 7 v v d d = 5 . 5 v 3 2 4 8 6 4 9 6 11 2 03876-021 figure 23 . wiper resistance vs. code vs. v dd v d d = 5 . 5 v v a = 5 . 0 v v b = 0 v v w c l k t a = 2 5 c r a b = 10 k ? f c l k = 100k h z 5 v 0 v 1 s / d i v 03876-022 figure 24 . digital feedthrough v dd = 5.5v v a = 5.0v v b = 0v code 0x40 to code 0x3f t a = 25 c r ab = 10k? v w 200ns/div 03876-023 figure 25 . midscale glitch, code 0x40 to code 0x3f v dd = 5.5v v a = 5.0v v b = 0v code 0x00 to code 0x7f t a = 25 c r ab = 10k ? v w 4s/div 03876-024 figure 26 . large signal settling time
ad5247 data sheet rev. f | page 12 of 20 test circuits figure 27 to figure 32 define the test conditions used in the specifications section. a w b du t v+ 03876-025 v+ = v d d 1 l sb = v+/ 2 n v m s figure 27 . potentiometer divider nonlinearity error (inl, dnl) v m s n o c o nn ec t a w b du t 03876-026 i w figure 28 . resistor position nonlinearity error (r - inl, r - dnl) v m s 2 a w b du t 03876-027 v m s 1 v w i w = v d d / r n o m i nal r w = [v m s 1 ? v m s 2 ]/ i w figure 29 . wiper resistance v+ = v dd 10% dut a w b v+ 03876-028 v ms v a v dd v ms % v dd % pssr (%/%) = figure 30 . power sup ply sensitivity (pss, pssr) w a b +15 v du t ?15 v v o u t o p2 7 v i n 03876-029 figure 31 . gain vs. frequency v d d a w b g n d i c m v c m n c du t n c 03876-030 figure 32 . common - mode leakage current
data sheet ad5247 rev. f | page 13 of 20 i 2 c interface the following abbreviations are used in this section: ? s = start condition ? p = stop condition ? a = acknowledge ? x = dont care ? w = write ? r = read ? a6, a5, a4, a3, a2, a1, a0 = address bits ? d6, d5, d4, d3, d2, d1, d0 = data bits table 6 . write mode s a6 a5 a4 a3 a2 a1 a0 w a x d6 d5 d4 d3 d2 d1 d0 a p slave address byte data byte table 7 . read mode s a6 a5 a4 a3 a2 a1 a0 r a 0 d6 d5 d4 d3 d2 d1 d0 a p slave address byte data byte sc l frame 1 slave address byte f r a me 2 d a t a b yt e start by master ac k by a d52 47 stop by master sd a r/w x d6 d4 d3 d2 d1 d0 1 1 9 ack by ad5247 1 9 d5 03876-032 a6 a4 a3 a2 a1 a0 ac k a5 figure 33 . writing to the rdac regis ter sc l frame 1 slave address byte frame 2 rdac register sta rt by master ac k by a d52 47 st o p b y ma st er s r / w 0 d6 d4 d3 d2 d1 d0 1 1 9 n o ac k b y ma st er 9 d5 03876-033 a6 a4 a3 a2 a1 a0 a5 figure 34 . reading from the rdac register table 8 . i 2 c slave addresses model slave addresses model slave address a6 a5 a4 a3 a2 a1 a0 a6 a5 a4 a3 a2 a 1 a0 ad5247bks5 -r2 0 1 0 1 1 1 0 ad5247bks50 -r l7 0 1 0 1 1 1 0 ad5247bks5 - rl7 0 1 0 1 1 1 0 ad5247bksz50 - rl7 0 1 0 1 1 1 0 ad5247bksz5 - rl7 0 1 0 1 1 1 0 ad5247bks100 -r2 0 1 0 1 1 1 0 ad5247bks10 - r2 0 1 0 1 1 1 0 ad5247bksz100 - r2 0 1 0 1 1 1 0 ad5247bks10 - rl7 0 1 0 1 1 1 0 ad5247bks100 - rl7 0 1 0 1 1 1 0 ad5247bksz10 - rl7 0 1 0 1 1 1 0 ad5247bksz100 - rl7 0 1 0 1 1 1 0 ad5247bksz10 - 1rl7 0 0 1 0 1 1 1 ad5247bksz100 - 1rl7 0 0 1 0 1 1 1 ad5247bksz10 - 2rl7 0 0 1 0 1 1 0 ad5247bksz100 - 2rl7 0 0 1 0 1 1 0 ad5247bks50 -r2 0 1 0 1 1 1 0
ad5247 data sheet rev. f | page 14 of 20 theory of ope ration the ad52 47 is a 128 - position, digitally - controlled variable resistor (vr) device. an internal power - on preset places the wiper at midscale during power - on, which simplifies the default condition recovery at power - up. programming the vari able resis tor rheostat operation the nominal resistance (r ab ) of the rdac between terminal a and terminal b is available in 5 k?, 10 k?, 50 k?, and 100 k?. the final t wo or three digits of the part number determine the nomin al resistance value; for example, 10 k? = 10 and 50 k? = 50. the r ab of the vr has 128 contact points accessed by the wiper terminal, plus the b terminal contact. the 7 - bit data in the rdac latch is decoded to select one of the 128 possible settings. assu ming a 10 k? part is used, the wipers fir st connection starts at the b terminal for data 0x00. because there is a 50 ? wiper contac t resistance, such a connection yields a minimum of 100 ? (2 50 ?) resistance between terminal w and terminal b. the second connection is the first tap point, corr esponding to 178 ? (r wb = r ab /128 + r w = 78 ? + 2 50 ?) for data 0x01. the third connection is the next tap point, representing 256 ? (2 78 ? + 2 5 0 ?) for data 0x02, and so on. each lsb data value incre ase moves the wiper up the resistor ladder unti l the last tap point is reached at 10,100 ? (r ab + 2 r w ). figure 35 shows a simplified diagram of the equivalent rdac circuit where the last resistor string is not accessed. bx wx ax d6 d4 d5 d2 d3 d1 d0 rdac latch and decoder r s r s r s 03876-034 figure 35 . ad5247 equivalent rdac circuit the general equation determining the digitally programmed output resistance between w and b is w ab wb r r d (d) r + = 2 128 (1) where: d is the decimal equivalent of the binary code loaded in the 7 - bit rdac register. r ab is the end - to - end resista nce. r w is the wiper resistance contributed by the on resistance of the internal switch. in summary, if r ab = 10 k? and the te rm in a l a is open - circuited, the output resistance r wb , shown in table 9 , is set for the indicated rdac latch codes. table 9 . codes and corresponding r wb resistance d (decimal) r wb (?) out put state 127 10, 0 72 full scale (r ab + 2 r w ) 64 515 0 midscale 1 228 1 lsb 0 150 zero scale (wiper contact resistance) note that in the zero - scale condition, a finite resistance of 100 ? between terminal w and terminal b is present. care should be t aken to limit the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between wiper w and terminal a also produces a digi tally controlled complementary resistance , r wa . when these terminals are used, th e terminal b can be opened. set the resistanc e value for r wa to start at a maximum value of resistance and to decrease the data loaded in the latch increases in value. the general equation for this operation is w ab wa r r d (d) r + ? = 2 128 128 (2) if r ab = 10 k? and the b terminal is open - c ircuited, the output resistance, r w a , shown in table 10 , is set for the indicated rdac latch codes. table 10. codes and corresponding r wa resistance d (decimal) r wa (?) output state 127 22 8 full scale 64 515 0 midscale 1 10,071 1 lsb 0 10, 1 5 0 zero scale typical device - to - device mat ching is process lot dependent and can vary by up to 30%. because the resistance element is processed in thin film technology, the change in r ab with temperature has a very low 45 ppm/c temperature coefficient.
data sheet ad5247 rev. f | page 15 of 20 programming the pote ntiometer divider vo ltage output operation the digital potentiometer easily generates a voltage divider at wiper - to - b and wiper - to - a , proportional to the input voltage at a - to - b. unlike the polarity of v dd to gnd, which mus t be positive, voltage across a - to - b, w - to - a, and w - to - b can be at either polarity. if ignoring the effect of the wiper resistance for approximation, connecting the terminal a to 5 v and the terminal b to ground produces an output voltage at the wiper - to - b starting at 0 v up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across terminal a and terminal b divided by the 128 positions of the potentiometer divider. the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to ter minal a and terminal b is a w v d d v = 128 ) ( (3) a more accurate calculation that includes the effect of wiper resistance, v w , i s a ab wb w v r (d) r (d) v = (4) operation of the digital potentiometer in the divider mode results in a more accurate operat ion over temperature. unlike rhe ostat mode, divider mode makes the output voltage mainl y on the ratio of internal resistor r wa to internal resistor r wb , and not the absolute values. therefore, the temperature drift reduces to 15 ppm/c. i 2 c - compatible 2 - w ire serial bus the first byte of the ad5247 is a slave address byte (see the i 2 c interface section ). it has a 7 - bit slave address and an r/ w bit. the 5 k and 50 k options support one 7 - bit slave address while t he 10 k and 100 k options each have three hard - coded slave address options available (see table 8 for a full list of slave address locations). the extra hard coded slave addresses on the 10 k and 100 k options allow users to e mploy up t o three of these d evices on one i 2 c bus. the seven msbs of the slave addres s are followed by 0 for a write command or 1 to place the device in read mode. the 2 - wire i 2 c serial bus protocol operates as follows: 1. the master initiates a data transf er by establishing a start condition, which is when a high - to - low transition on the sda line occurs while scl is high (see figure 33 ). the following byte is the slave address byte, consisting of the 7 - bit slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). the slave , whose address corresponds to the transmitted address , responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master reads from the slave device. if the r/ w bit is low, the master writes to the slave device. 2. in write mode, after acknowledgement of the slave address byte, the next byte is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight da ta bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 33). 3. in read mode, after acknowledgment of the slave addr ess byte, data is received over the serial bus in sequences of nine clock pulses (a slight difference from write mode, where eight data bits are followed by an acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 34). 4. when all data bits have been read or written, a stop con - dition is established by the master. a stop condition is defined as a low - to - high transition on the sda line while scl is high. in write mode, the master pulls the sda line high d uring the 10 th clock pulse to establish a stop condi tion (see figure 33 ). in read mode, the master issues a n o a cknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse, which goes high to establish a stop condition (see figure 34). a repeated write function gives the user flexibility to update the rdac output a number of times after addressing the part only once. for example, after the rdac has acknowledged its slave address in the write mode, the rdac output updates on each successive byte. if different instructions are needed, the write/read mode has to start again with a new slave address and data byte. similarly, a repeated read function of the rdac is also allowed.
ad5247 data sheet rev. f | page 16 of 20 level shifting for b idirectional interfa ce while most legacy systems can be operated at one voltage, a new component can be optimi zed at another voltage. when two systems operate the same signal at two different voltages, proper level shifting is needed. for instance, users can employ a 3.3 v e 2 prom to interface with a 5 v digital potentiometer. a level shifting scheme is needed to enable a bidirectional commu - nication so that the setting of the digital potentiometer can be stored in and retrieved from the e 2 prom. figure 36 shows one of the level - shifting implemen tations. m1 and m2 can be any n - channel signa l fets, or if v dd falls below 2.5 v, m1 and m2 can be low threshold fets such as the fdv301n. e 2 pr o m ad 524 7 sda 1 sc l 1 d g r p r p 3 . 3 v 5 v s m1 sc l 2 sda 2 r p r p g s m2 v dd1 = 3 . 3 v v dd2 = 5 v d 03876-035 figure 36 . level - shifting for operation at different potentials esd protection all digital inputs are protected with a series input res istor and parallel zener esd structures as shown in figure 37 . this applies to digital input pins (sda and scl). 340? gnd 03876-036 logic sda/ scl figure 37 . esd protection of digital pins terminal voltage ope rating range the ad5247 v dd and gnd power supply defines the boundary conditions for proper 3 - terminal digital potentiometer operation. suppl y signals present on terminal a and terminal w that excee d v dd or gnd are clamped by the internal forward biased diodes (see figure 38). a v d d w g n d 03876-038 figure 38 . maximum terminal voltages set by v dd and gnd maximum operating cu rrent at low code values, the user should be aware that, due to low resistance values, the current through the rdac might exceed the 5 ma limit. in figure 39 , a 5 v supply is placed on the wip er, and the current through terminal w and terminal b is plotted with respect to code. a li ne is also drawn denoting the 5 ma current limit. note that at low code values (particularly for the 5 k and 10 k options), the current level increases signifi - cantly. care should be taken to limit the current flow between w and b in this state to a maximum continuous current of 5 ma and a maximum pulse current of no more than 20 ma. otherwise, degradatio n or possible destruction of the internal switch contacts can occur. code (decimal) i wb current (ma) 0 0.01 0.1 1 10 16 32 48 64 80 96 1 12 128 100 5ma current limit r ab = 5k? r ab = 10k? r ab = 100k? r ab = 50k? 03876-039 figure 39 . maximum operating current power - up sequence because the esd protection diodes limit the voltage compliance at terminal a and terminal w (see figure 38 ), it is important to power v dd /gnd before applying any voltage to terminal a and terminal w; otherwise, the diode is forward - biased such that v dd is powered unintentionally and can affect the rest of the users circuit. the idea l power - up sequence is in the following order: gnd, v dd , digital inputs, v a , and v w . the relative order of powering v a and v w and the digital inputs is not important as long as they are powered after v dd /gnd.
data sheet ad5247 rev. f | page 17 of 20 layout and power sup ply bypassing it is good practice to employ a compact, minimum lead - length layout design. the leads to the inputs should be as direct as pos - sible with minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is good practice to bypass th e power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with 0.01 f to 0.1 f disc or chip ceramic capacitors. low esr 1 f to 10 f tantalum or electrolytic capaci - tors should also be applied at the s upplies to minimize any transient disturbance and low frequency ripple (see figure 40 ). note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. ad5247 v dd c1 0.1f c3 10f gnd + v dd 03876-040 figure 40 . power supply bypassing constant bias to ret ain resistance setti ng for user s who desire nonvolatility but cannot justify the addition al cost for the eemem , the ad5247 can be considered a low cost alternative because it maintains a const ant bias to retain the wiper setting. the ad5247 is specifically designed with low power in mind, which allows low power consumption even in battery - operated systems. figure 41 demonstrates the power consumption from a 3.4 v 450 ma/hr li - ion cell phone battery, which is connected to the ad5247. the measurement over time shows that the device draws approximately 1.3 a and consumes negligible power. over a course of 30 days, the battery was depleted by less than 2%, the majority of which was due to the intrinsic leakage current of the battery itself. da ys b a tte r y life depleted 0 90 % 92 % 94 % 96 % 5 1 0 1 5 98 % 100 % 102 % 104 % 106 % 108 % 1 10 % 2 0 2 5 3 0 t a = 2 5 c 03876-041 figure 41 . battery operating life depletion this demonstrates that constantly biasing the potentiometer is a practical approach. most portable devices do not require the removal of batteries for charging. although the resistance setting of the ad5247 is lost when the battery needs replace - ment, such events occur rather infrequently. as a result, this inconvenience is justified by the lower cost and smaller si ze offered by the ad5247. if total power is lost, the user should be provided with a means to adjust the setting accordingly.
ad5247 data sheet rev. f | page 18 of 20 outline dimensions 1.30 bsc compliant to jedec standards mo-203-ab 1.00 0.90 0.70 0.46 0.36 0.26 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 072809-a 0.10 max 1.10 0.80 0.40 0.10 0.22 0.08 3 12 4 6 5 0.65 bsc coplanarity 0.10 seating plane 0.30 0.15 figure 42. 6-lead thin shrink small outline transistor package [sc70] (ks-6) dimensions shown in millimeters ordering guide model 1 r ab (k) temperature range package description 2 package option branding ad5247bksz5-rl7 5 C40c to +125c 6-lead thin shrink small outline transistor package [sc70] ks-6 d96 ad5247bksz10-rl7 10 C40c to +125c 6-lead thin shrink small outline transistor package [sc70] ks-6 d95 ad5247bksz10-1rl7 10 C40c to +125c 6-lead thin shrink small outline transistor package [sc70] ks-6 d5e ad5247bksz10-2rl7 10 C40c to +125c 6-lead thin shrink small outline transistor package [sc70] ks-6 dak ad5247bksz50-rl7 50 C40c to +125c 6-lead thin shrink small outline transistor package [sc70] ks-6 d97 ad5247bksz100-r2 100 C40c to +125c 6-lead thin shrink small outline transistor package [sc70] ks-6 d98 ad5247bksz100-rl7 100 C40c to +125c 6-lead thin shrink small outline transistor package [sc70] ks-6 d98 ad5247bksz100-1rl7 100 C40c to +125c 6-lead thin shrink small outline transistor package [sc70] ks-6 daj ad5247bksz100-2rl7 100 C40c to +125c 6-lead thin shrink small outline transistor package [sc70] ks-6 dal EVAL-AD5247DBZ evaluation board 1 z = rohs compliant part. 2 the evaluation board is shipped with the 10 k r ab resistor option; however, the board is compatible with all available resistor value options.
data sheet ad5247 rev. f | page 19 of 20 notes
ad5247 data sheet rev. f | page 20 of 20 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2003 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03876 - 0- 5/12(f)

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